What the 1:6 LVCMOS fan-out buys you
The CDCLVC1106PWR is a single-input, six-output fanout buffer designed to distribute a LVCMOS clock without adding a differential pair. The 250 MHz max frequency covers most FPGA reference clocks, SERDES reference inputs, and logic synchronisation trees that run on single-ended signals.
The 14-TSSOP package is a 4.40 mm-wide body — fits on a two-layer board with 0.65 mm pitch, but the fan-out traces need impedance control if the routed length exceeds a few inches.
ROHS3 compliant, no exemptions that complicate EU or California compliance. The 14-TSSOP is a common footprint; no package scarcity risk.