PLL clock conditioner with 1.5 GHz output ceiling
The Texas Instruments CDCE72010RGCRG4 is a PLL-based clock synchronizer, fanout buffer, and jitter cleaner that accepts up to three independent reference inputs (LVCMOS, LVDS, or LVPECL) and distributes them across twenty differential outputs running at up to 1.5 GHz. The 3:20 input-to-output ratio makes it a dense fanout solution for backplanes, wireless base station cards, and high-speed data converter clock trees where one device replaces multiple smaller fanout buffers.
TI lists the CDCE72010RGCRG4 with an active product status. For production builds that already qualify this device, the supply channel is stable through standard distribution and independent sourcing.
Differential I/O and 64-VFQFN footprint
All input and output paths support differential signalling (Yes/Yes in the differential I/O field), which is expected for a 1.5 GHz clock fanout — single-ended routing at that frequency would suffer excessive radiated emissions and skew.