250 MHz 1:8 HCSL fanout buffer
The CDCDB803RSLR is a 1:8 clock buffer from Texas Instruments that accepts one HCSL input and delivers eight HCSL outputs, each running up to 250 MHz. The differential HCSL signalling keeps edge rates clean for PCIe reference clocks, Ethernet PHY masters, and FPGA reference distribution.
The supply rail accepts 3V to 3.6V, so a nominal 3.3V rail with ±5% tolerance stays inside the window without an extra regulator.
48-VQFN package and reflow considerations
Standard lead-free reflow profile applies; no exotic process steps needed.
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