What this 74HCT latch is and where it fits
This part is rated from -55°C to 125°C. The 35ns propagation delay is moderate for 5V HCT. Output drive is 6mA source and 6mA sink.
Lifecycle and sourcing reality
The CD74HCT373M carries an Active lifecycle status and is ROHS3 compliant. For a BOM line that needs a 5V transparent latch in SOIC-20, this is a straightforward, low-risk procurement.
35ns propagation delay — what it means for the bus
The 35ns propagation delay is the time from the latch-enable or data input edge to a valid output, measured at the rated supply and load. In a typical address-latching application, this delay eats into the memory access window: if the CPU drives the address bus and asserts LE, the latch outputs settle 35ns later. That leaves the remaining cycle time for the memory device to respond. For a 50ns SRAM on a 100ns bus cycle, the margin is tight but workable. For faster processors or pipelined buses, a faster latch family (like 74FCT with 8.5ns delay) would be needed — but that comes with a narrower temperature range.