Quad buffer with 3-state outputs for bus-oriented logic
The 3-state outputs allow multiple buffers to share a common data bus without contention, a common requirement in microprocessor interface and memory-address decoding circuits.
Each buffer can source or sink 6mA of output current, which is the standard HCT drive level for driving one or two LSTTL loads or a CMOS input. The 3-state outputs go high-impedance when the associated output-enable pin is low, letting you wire-OR multiple CD74HCT126M devices onto a shared data or address bus. The non-inverting path means the output follows the input logic level — no polarity inversion to track in the schematic.
The 74HCT series remains a widely stocked logic family across the distribution channel.
14-SOIC footprint — board-level fit
Housed in a 14-SOIC package with a 3.90mm body width (the narrow SOIC-14 variant), the CD74HCT126M is a surface-mount device that fits the standard JEDEC SOIC-14 land pattern. The 0.154-inch (3.90mm) width is the same footprint used by the majority of 14-pin SOIC logic parts, so a board already laid out for a 74HCT125 or 74HCT00 will accept this buffer without a layout change.