Propagation delay and timing margin
The CD74HCT10M96: At 4.5V with a 50pF load the propagation delay is 24ns. That is the number to check against your bus timing closure — if your clock period allows 30ns or more for gate delay, this part has comfortable margin. At higher capacitive loads the delay will increase; the datasheet curve (not reproduced here) shows the derating, so keep the 50pF figure as your baseline for fan-out planning.
Temperature grade and deployment environments
The 14-SOIC body is narrow (3.90 mm width), which saves board area compared to the wider SOIC-14 variant, but the thermal performance is identical — the package dissipation is limited by the 4mA output current, not the case size.