7-stage binary ripple counter with a 35 MHz ceiling
The CD74HC4024E is a 7-stage binary ripple counter from TI's 74HC family, designed to divide an input clock by powers of two up to 128. The 35 MHz count rate sets the maximum input frequency the internal flip-flop chain can reliably toggle — useful for frequency division, time-base generation, or event counting in industrial and telecom logic chains. Asynchronous reset (active high) clears all stages immediately, independent of the clock, which matters when you need a deterministic reset without waiting for a clock edge.
Wide supply and military temperature range
At 125°C junction, propagation delays will stretch — budget extra timing margin if the input clock is near the 35 MHz limit at high temperature.
Through-hole 14-DIP — still in active production
For designs that need a through-hole binary counter in a 14-DIP footprint — common in breadboard prototyping, legacy board repairs, or low-volume industrial controllers — this part is still a standard catalog item, not a phase-out risk.