24 MHz synchronous up/down decade counter in a 16-SOIC
The CD74HC192NSR is a 74HC-series synchronous up/down decade counter in a 16-SOIC surface-mount package. It counts clock edges on a single 24 MHz input, with separate up and down count directions.
At 24 MHz, the counter can track a 24 MHz clock edge every ~41.7 ns. In a typical application like a frequency divider or event counter, that sets the maximum input frequency before the counter misses edges. The positive-edge trigger means the count advances on the rising edge of the clock — make sure the upstream driver's output transitions cleanly through the logic threshold at 24 MHz. With a 2 V supply the propagation delay increases, so budget extra timing margin if running near the speed limit at low voltage.
Asynchronous reset — no clock needed to clear
The asynchronous reset (active-high) forces all four bits to zero regardless of the clock state. This is the reset to use for power-up initialization or for a hard reset in a fault condition — no need to wait for the next clock edge. In a system where the clock might be gated or missing, the async reset guarantees the counter starts from a known state.