Dual JK flip-flop with reset — 60 MHz, 2 V to 6 V, through-hole DIP-14
The Texas Instruments CD74HC107E is a dual JK flip-flop in the 74HC logic family. Each of the two elements stores one bit, triggered on the negative edge of the clock, with complementary outputs (Q and /Q) and an active-low reset input. It runs from a 2 V to 6 V supply and clocks at 60 MHz, making it a straightforward choice for counter, divider, and register applications in 5 V and 3.3 V systems that need a clean edge-triggered storage element.
60 MHz clock and 29 ns propagation delay — timing margin for the bus
The 60 MHz maximum clock frequency and 29 ns max propagation delay at 6 V, 50 pF load set the timing budget. At 5 V operation the delay is slightly longer than the 6 V figure — typical for HC logic — so the 29 ns number is the cleanest corner. For a 10 MHz system clock, the delay leaves plenty of margin; at 30 MHz the designer should check setup/hold against the driving device's output timing. The negative-edge trigger means the flip-flop captures data on the falling clock edge, which can simplify clock-domain crossings if the preceding stage outputs on the rising edge.
Military temperature range and 4 µA quiescent current
Rated -55°C to 125°C, the CD74HC107E covers military and industrial environments — avionics, downhole, outdoor telecom, engine bay — where commercial-grade logic would drift or fail. Quiescent current is just 4 µA, so in a battery-backed or always-on subsystem the static draw is negligible. Output drive is 5.2 mA source and sink, typical for HC logic; it can drive a few LS TTL inputs or a CMOS load directly, but for a heavy fan-out or a long trace a buffer is advisable.
Through-hole DIP-14 — prototyping and legacy socket compatibility
The CD74HC107E comes in a 14-pin DIP (0.300" body, 7.62 mm pitch) with a 14-PDIP supplier package. This is the classic through-hole footprint that fits breadboards, prototyping boards, and existing socketed designs. For new builds with surface-mount assembly, look at the SOIC-14 variant of the same function. Input capacitance is 10 pF, which is standard for HC logic and won't load a typical CMOS or TTL output significantly.
Active lifecycle — no EOL risk for production
Texas Instruments lists the CD74HC107E as Active with ROHS3 compliance. There is no last-time-buy notice or obsolescence flag. For volume or scheduled orders, the supply posture is stable — no need to qualify a second source unless dual-sourcing policy requires one.