Octal D flip-flop with master reset for high-speed logic
The CD74ACT273M96 is an octal D-type flip-flop from the 74ACT family, featuring a master reset input that clears all eight flip-flops asynchronously when pulled low. Positive-edge triggered, it clocks data from D inputs to non-inverted Q outputs at up to 80 MHz (cite:). Each output can sink or source 24 mA (cite:), enough to drive standard TTL loads, bus lines, or LED indicators without external buffers. The quiescent current sits at 8 µA (cite:), keeping standby power low in battery-backed or power-sensitive designs.
Timing and temperature grade for harsh environments
Propagation delay is 13.5 ns max at 5V supply with a 50 pF load (cite:) — this sets the timing budget for synchronous interfaces in backplane or memory-mapped I/O applications. The 10 pF input capacitance (cite:) helps maintain signal integrity on high-speed clock trees.
Active production and sourcing posture
Volume pricing and lead time are confirmed per RFQ — no stock-holding claim, sourced to order.