D-Type flip-flop with master reset
The CD74ACT175M96 is a single-element, 4-bit D-type flip-flop from the 74ACT family, clocked at 114 MHz on a positive edge. It includes a master reset function that clears all outputs asynchronously, and complementary outputs (Q and Q-bar) per bit. The 16-SOIC package (0.154-inch body width) is surface-mount and fits a standard SOIC-16 footprint. Quiescent current is 8 µA typical, and output drive is 24 mA source/sink at the rated supply.
Temperature range and timing margins
The propagation delay is 11.5 ns maximum at 5 V into a 50 pF load — that delay sets the setup/hold budget for the receiving register in a clocked bus. Input capacitance is 10 pF per input, which loads the driving gate by that amount; in a high-fanout clock tree, the cumulative capacitance must stay within the driver's specified limit to avoid edge-rate degradation.