The CD74AC623M is an 8-bit non-inverting transceiver from the 74AC family, with 3-state outputs and 24 mA symmetrical drive at both high and low levels.
24 mA drive — enough for a loaded backplane segment
The 24 mA output current (both source and sink) is the standard 74AC drive level. It handles a moderate backplane trace or a few CMOS loads without needing a buffer. If your bus has more than eight or ten loads, or runs a long cable, you will want to check the DC fan-out against the input current of the receivers. At 5 V the drive is comfortable; at 1.5 V the output resistance rises, so the actual delivered current into a short will be lower — budget for that if running near the minimum supply.
Single-element, 8-bit — one package, one bus direction control
A single element with eight bits per element means one DIR pin controls the direction of all eight channels. The 3-state output enable (OE) lets you float the bus when the transceiver is not driving. This is the classic 74AC623 function: non-inverting, so the data polarity stays the same from A to B or B to A. No inversion to track in the logic design.
20-SOIC wide-body — footprint and thermal note
The 20-SOIC package with 7.50 mm body width (0.295″) is the wide SOIC variant, not the narrow 5.3 mm version. The pad layout matches the standard 20-SOIC wide footprint. Surface-mount assembly with MSL 1 or 2 typical for 74AC logic — no special bake required unless the moisture barrier bag has been open for an extended period. The wide body helps with manual inspection and rework.