Dual JK flip-flop for high-speed logic — 100 MHz clock, military temp range
Timing budget — 10.3 ns propagation delay at 5 V
Max propagation delay of 10.3 ns at 5 V with a 50 pF load sets the timing closure window for back-to-back flip-flop stages or cascaded counters. Input capacitance is 10 pF, typical for 74AC inputs, so fan-out calculations should account for that load per driven gate.
Package and mounting — 16-pin DIP, through hole
Housed in a 16-pin DIP (0.300", 7.62 mm body, PDIP-16), the CD74AC109E is a through-hole part for prototyping, legacy board repairs, or designs where socketed ICs are preferred for field service. The supplier device package is 16-PDIP.
Marked as active in the lifecycle stage with no NRND or EOL flags, this part remains in standard production. ROHS3 compliant, no exemption issues for EU or California markets.