24-stage divide-by-2 frequency divider for timing and clock division
The Texas Instruments CD4521BMT is a 24-stage divide-by-2 frequency divider from the 4000B series, packaged in a 16-SOIC surface-mount package. It accepts a negative-edge clock input and provides a divided output, with an asynchronous reset to clear the internal counter.
The 13 MHz maximum count rate defines the highest input clock frequency the CD4521BMT can reliably divide. For a 24-stage divider, the output frequency is the input divided by 2^24.
Asynchronous reset — no clock needed to clear
The reset is asynchronous, meaning asserting the reset pin immediately clears all 24 stages regardless of the clock state. This is useful for power-on initialization or emergency reset without waiting for a clock edge. No pull-up or pull-down is required on the reset pin if driven by a logic output; an open-drain or mechanical switch needs an external resistor to VDD or VSS to avoid floating.
The supply range is 3 V to 18 V, typical of 4000B CMOS logic.