What the 3V to 18V supply range buys the design
Each gate draws a maximum 4µA quiescent current, so the part can sit on an always-on power domain without draining the backup battery.
Output drive and fan-out — the asymmetry to budget for
The output stage delivers 4.3mA sourcing and 24mA sinking. That 5.6:1 ratio means the CD4049UBDR can drive a heavier pull-down load than pull-up — useful when interfacing to open-drain buses or driving the base of an NPN transistor, but a constraint if you need symmetric drive into a terminated transmission line. The 50ns propagation delay at 15V and 50pF is the timing ceiling; at lower supply voltages the delay stretches, so a timing closure check is needed if the part runs at 5V in a 1MHz control loop.
Package and footprint — what the SOIC-16 tells the layout
The CD4049UBDR is supplied in a 16-SOIC body, 3.90mm width, surface-mount only. The 1.27mm pin pitch is standard for automated assembly and rework.
The date-code and marking should trace cleanly to TI's authorized chain — any lot with inconsistent laser etch or mismatched font on the package body warrants a decap check before accepting it on a production line.