Dual JK flip-flop in 16-TSSOP — 24 MHz, 3V–18V rail
The CD4027BPWR is a dual JK flip-flop from the 4000B series, with Set and Reset inputs, positive-edge triggering, and complementary outputs. Each element stores one bit, and the device toggles up to 24 MHz across a 3V to 18V supply range — a wide operating window that suits battery-powered or unregulated rail designs where the logic must keep running as the supply sags. The quiescent current is only 4 µA typical, making this flip-flop a low-overhead choice for power-sensitive boards where the logic block is always biased but rarely switches.
Propagation delay and output drive — 90 ns at 15V, 50 pF
Maximum propagation delay is 90 ns at 15V supply with a 50 pF load — a figure that matters when timing closure is tight in a multi-stage counter or shift register. The complementary outputs each source or sink 6.8 mA, enough to drive a downstream CMOS gate input or a low-current LED indicator without a buffer. Input capacitance is 5 pF per input, so the upstream driver sees a light load — fan-out is generous even from a 4000B-series output.