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STMicroelectronics STM32L443CCF6TR — Microcontrollers & Processors (MCU / MPU / DSP)

STM32L443CCF6TR ARM Cortex-M4 MCU, 80MHz, 256KB Flash, WLCSP

MPNSTM32L443CCF6TR
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STMicroelectronics STM32L4 series STM32L443CCF6TR, ARM Cortex-M4 32-Bit Single-Core MCU, 80MHz, 256KB Flash, 64K x 8 RAM, 49-UFBGA WLCSP, -40°C~85°C, 1.71V~3.6V.

$4.2040Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

STM32L443CCF6TR specifications
ParameterValue
SeriesSTM32L4
MountingSurface Mount
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))1.71V ~ 3.6V
Operating temperature-40°C~85°C(TA)
Speed80MHz
PackageTape & Reel (TR)
RAM size64K x 8
Core size32-Bit Single-Core
PeripheralsBrown-out Detect/Reset, DMA, LCD, PWM, WDT
ConnectivityCANbus, I²C, IrDA, LINbus, MMC/SD, QSPI, SAI, SPI, SWPMI, UART/USART, USB
Number of i (O)83
Core processorARM® Cortex®-M4
Case49-UFBGA, WLCSP
Data convertersA/D 16x12b; D/A 2x12b
Program memory size256KB (256K x 8)

Product details

49-ball WLCSP — footprint trade-offs

This variant ships in a 49-ball wafer-level chip-scale package (WLCSP) measuring 3.14 x 3.13 mm, the smallest footprint in the STM32L443 family. The trade-off: WLCSP requires tighter PCB land patterns, controlled solder-paste volume, and X-ray inspection after reflow. It is not hand-solderable — plan for an automated SMT line. The 83 I/O count is available in this package, so peripheral-rich designs do not lose GPIO density despite the tiny body.

Brown-out detect, DMA, and a watchdog timer are on-chip, reducing external supervisor IC count.

Frequently asked questions

What is the difference between STM32L443CCF6TR and STM32L443CCT6?

The primary difference is the package: the STM32L443CCF6TR uses a 49-ball WLCSP (3.14 x 3.13 mm), while the STM32L443CCT6 uses an LQFP-48 package with gull-wing leads. The WLCSP saves board area but requires an SMT line with X-ray inspection; the LQFP variant is easier to hand-solder and rework. Core, memory, and peripheral sets are otherwise identical.