80 MHz Cortex-M4 with FPU — why not the 32 MHz Cortex-M3 sibling
The STM32L412CBT6P: 128 KB Flash and 40 KB SRAM.
Product status is Active, ROHS3 Compliant.
38 I/O and Quad SPI — peripheral mix for sensor-heavy designs
38 I/O lines in a 48-LQFP package (7x7 mm body).
The 48-LQFP package is a standard JEDEC footprint — no BGA reflow complexity, and hand-solderable for prototypes.
