84 MHz Cortex-M4 in a wafer-level CSP — what that buys the board
That footprint is the smallest in the STM32F4 family, which matters when board area is the constraint — wearable, sensor hub, or compact motor-drive feedback boards. The 32-bit single-core processor includes a single-cycle multiply and hardware divide, plus a floating-point unit, so sensor fusion or PID loops run without software emulation overhead. The 36 GPIOs in this package limit parallel bus expansion, but for a serial-centric design the pin count is adequate.
Lifecycle and sourcing — active, but check the package
The WLCSP package is not a standard JEDEC footprint — it requires a stencil design matched to the 0.4 mm ball pitch and careful reflow profiling. For volume builds, confirm the PCN status on the base number STM32F401; ST has migrated some F4 variants to newer nodes, but this order code remains in the active portfolio.