The STM32F373VBH6: ROHS3 compliant per the manufacturer's declaration, which covers the current EU RoHS exemption list.
72 MHz Cortex-M4 with mixed-signal ADC — the fit decision
128 KB of Flash and 24K x 8 (192 Kbit) SRAM is modest by current standards — budget the application code, HAL, and RTOS footprint against the 128 KB ceiling. The 24K SRAM includes the 8 KB core-coupled memory region accessible without wait states; the remaining 16 KB is the general-purpose SRAM1 block. A firmware image that exceeds 100 KB leaves little headroom for field-update staging buffers.
100-UFBGA 7x7 mm — board integration constraints
The 100-UFBGA package measures 7x7 mm with a 0.50 mm ball pitch. The supplier device package is 100-UFBGA (7x7), so the footprint matches the STM32F373VxT6 and STM32F303VxT6 variants in the same package — a layout reuse opportunity if the BOM swaps between those parts. 84 I/O lines are brought out from the 100-ball array. The remaining 16 balls are power, ground, and the two oscillator inputs.
Industrial temperature grade and peripheral set
No AEC-Q100 grade is claimed; this is not an automotive-qualified part. Connectivity includes CANbus (one CAN 2.0B controller), USB (device only, no OTG), I²C, SPI, UART/USART with IrDA and LIN support. The peripheral set is identical to the STM32F303 series — the DMA controller and PWM timers are shared across the STM32F3 family. The I²S peripheral is present for audio codec interfaces.