512 KB Flash, 64 KB SRAM — memory budget for mixed-signal control
Its core runs at 72 MHz, with a single-cycle multiply and hardware divide, plus a single-precision FPU and DSP instructions for sensor fusion or motor-control loops. Program memory is 512 KB of Flash, backed by 64 KB SRAM — enough headroom for a Modbus stack, a USB CDC virtual COM port, and a 1 kHz current-control ISR without overflow into external memory.
Peripheral set — CAN, USB, and multiple serial buses on one die
Package and mounting — 64-LQFP, 10x10 mm body
Housed in a 64-LQFP with a 10x10 mm body and 0.5 mm pitch, this part reflows on standard FR-4 with a single-sided placement pass. The exposed pad is not present on this package variant — thermal dissipation relies on the leadframe and copper pours under the body. Surface-mount assembly is straightforward for any line equipped for 0.5 mm pitch QFPs.