The STM32F101ZDT6: ARM Cortex-M3 core at 36 MHz, 384 KB Flash, 48 KB RAM, 144-LQFP, -40°C to 85°C.
The 36 MHz ceiling on the Cortex-M3 core is the main differentiator versus the STM32F103 sibling that runs at 72 MHz. For a control loop that samples a 16-channel 12-bit ADC at moderate rates, or a UART/I²C/SPI bridge handling sensor data, 36 MHz is sufficient and keeps the BOM cost lower. The flash wait state stays at zero for most of the clock range, so instruction fetch doesn't stall — a practical benefit when the code is tight and the interrupt latency budget is a few microseconds. If your algorithm needs heavy number crunching or high-speed data streaming, the 72 MHz STM32F103ZDT6 is the pin-compatible upgrade path.
Memory sizing for the firmware budget
384 KB of Flash and 48 KB of SRAM set a clear boundary for the firmware image and runtime data. The 48 KB SRAM handles a few large buffers — for example, a UART DMA ring buffer plus a display frame buffer — but if your design needs more than that, you will need to move to a part with larger RAM or add external SRAM. The 48K x 8 notation means 48 KB organised as 8-bit words, which is the standard ARM byte-addressable layout.
The 144-LQFP (20x20 mm) package gives access to 112 I/O pins, enough for parallel LCD interfaces, external memory buses, or a dense sensor array.
