Dual UART with 64-byte FIFO in 48-LQFP
The SC16C752BIB48,128 is a dual-channel UART (DUART) from NXP, integrating two independent universal asynchronous receiver-transmitter channels with a 64-byte FIFO per channel, modem control, auto flow control, and false start bit detection.
5 Mbps data rate and 64-byte FIFO depth
The 5 Mbps maximum data rate supports high-speed serial links such as RS-232, RS-485, or custom asynchronous protocols where per-bit timing at 200 ns is required. The 64-byte FIFO per channel reduces CPU interrupt load by buffering up to 64 received bytes before asserting an interrupt — useful in systems with bursty serial traffic or where the processor cannot service each byte individually. With modem control (CTS/RTS), auto flow control, and false start bit detection on both channels, the SC16C752BIB48,128 handles full-duplex handshaking autonomously, offloading the host processor from managing flow control at the protocol level.
48-LQFP (7x7 mm) surface-mount package
Housed in a 48-LQFP package measuring 7x7 mm, the SC16C752BIB48,128 uses a 0.5 mm pitch lead frame.
Active lifecycle and ROHS3 compliance
It is ROHS3 compliant, meeting the EU RoHS directive for lead-free and restricted-substance restrictions. No PCN or LTB has been issued for this order code, supporting its use in new designs without near-term obsolescence risk.