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NXP USA Inc. MKL26Z128VLH4 — Microcontrollers & Processors (MCU / MPU / DSP)

NXP MKL26Z128VLH4 — 32-bit ARM Cortex-M0+ MCU, 48MHz, 128KB Flash, USB OTG

MPNMKL26Z128VLH4
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NXP Kinetis KL2 series, 32-bit ARM Cortex-M0+ at 48MHz, 128KB Flash / 16KB SRAM, USB OTG + full peripheral set, 1.71 to 3.6V supply, -40 to 105°C, 64-LQFP tray.

$7.1600Ref. price · indicative, final on quote
Packaging64-LQFP
StockContact for availability
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

MKL26Z128VLH4 Technical Specifications
ParameterValue
SeriesKinetis KL2
Mounting typeSurface Mount
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))1.71V ~ 3.6V
Operating temperature-40°C ~ 105°C (TA)
Speed48MHz
PackageTray
RAM size16K x 8
Core size32-Bit Single-Core
PeripheralsBrown-out Detect/Reset, DMA, I²S, LVD, POR, PWM, WDT
ConnectivityI²C, LINbus, SPI, UART/USART, USB, USB OTG
Number of i (O)50
Core processorARM® Cortex®-M0+
Case64-LQFP
Data convertersA/D - 16bit; D/A - 12bit
Program memory size128KB (128K x 8)

Frequently asked questions

Can I use the internal oscillator for USB full-speed without an external crystal?

The part carries an internal 48MHz oscillator and lists USB OTG as a core peripheral. The datasheet oscillator accuracy section specifies the tolerance needed for USB full-speed; verify it meets the USB-IF timing window for your target region before removing the crystal.

What supply voltage does the MKL26Z128VLH4 need?

1.71 to 3.6V. This is a 3.3V nominal part with a 1.71V lower floor — not 5V tolerant. Plan a regulator if the board rail is 5V.

What is the temperature rating?

-40 to 105°C ambient (TA). At the upper end of that range, model package thermal resistance against actual I/O and core loading rather than applying a generic derating assumption.