NXP Kinetis K20, MK20DN512VLL10, ARM Cortex-M4 32-bit single-core at 100 MHz, 512 KB FLASH, 128 KB SRAM, 66 GPIO, 33-channel 16-bit ADC and 1-channel 12-bit DAC, USB OTG and CANbus, 1.71–3.6 V, −40 to 105 °C, supplied in tray, 100-LQFP (14×14 mm).
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Specifications
| Parameter | Value |
|---|---|
| Series | Kinetis K20 |
| Mounting type | Surface Mount |
| Oscillator type | Internal |
| Program memory type | FLASH |
| Voltage - supply (Vcc (Vdd)) | 1.71V ~ 3.6V |
| Operating temperature | -40°C ~ 105°C (TA) |
| Speed | 100MHz |
| Package | Tray |
| RAM size | 128K x 8 |
| Core size | 32-Bit Single-Core |
| Peripherals | DMA, I²S, LVD, POR, PWM, WDT |
| Connectivity | CANbus, EBI/EMI, I²C, IrDA, SD, SPI, UART/USART, USB, USB OTG |
| Number of i (O) | 66 |
| Core processor | ARM® Cortex®-M4 |
| Case | 100-LQFP |
| Data converters | A/D 33x16b; D/A 1x12b |
| Program memory size | 512KB (512K x 8) |
Frequently asked questions
Does the single 12-bit DAC meet the accuracy needs of an analog output retrofit?
At 3.3 V supply the 12-bit DAC resolves 0.81 mV per LSB. Meeting a ±0.5% accuracy target at full scale requires total error — including offset, gain error, and temperature drift — to stay within ±16.5 mV across the operating temperature range. Resolution alone does not guarantee accuracy; the spec table lists only the converter resolution, not the overall error budget, so the firmware and system-level calibration path matters as much as the DAC rating.
Is USB OTG on this part configurable for host mode without an external PHY?
The USB OTG peripheral is present and supports the OTG protocols, but the internal PHY capability (full-speed only, no high-speed) and the host/device pin-strap configuration are detailed in the NXP datasheet rather than in the short-form spec table. Verify host-mode feasibility and the ±0.25% clock accuracy requirement for full-speed USB against the full datasheet before committing the USB port to a host role.