NXP i.MX RT1050 series, 32-bit ARM Cortex-M7 at 528MHz, 512KB SRAM, external program memory interface, 196-ball MAPBGA (12×12mm), 3V–3.6V supply, -40°C to 105°C junction, 127 GPIO, Ethernet/CAN/USB OTG, 20×12-bit ADC, Active ROHS3.
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Specifications
| Parameter | Value |
|---|---|
| Series | RT1050 |
| Mounting type | Surface Mount |
| Oscillator type | External, Internal |
| Program memory type | External Program Memory |
| Voltage - supply (Vcc (Vdd)) | 3V ~ 3.6V |
| Operating temperature | -40°C ~ 105°C (TJ) |
| Speed | 528MHz |
| Package | Tray |
| RAM size | 512K x 8 |
| Core size | 32-Bit Single-Core |
| Peripherals | Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT |
| Connectivity | CANbus, EBI/EMI, Ethernet, I²C, MMC/SD/SDIO, SAI, SPDIF, SPI, UART/USART, USB OTG |
| Number of i (O) | 127 |
| Core processor | ARM® Cortex®-M7 |
| Case | 196-LFBGA |
| Data converters | A/D 20x12b |
Frequently asked questions
Is the MIMXRT1052CVJ5B footprint-compatible with the RT1051?
Both share the same 196-ball MAPBGA package, but the RT1051 carries 256KB SRAM versus 512KB on this part — the package footprint is mechanically compatible, but verify your PCB layout supports the SRAM density and memory-controller routing for your chosen external memory device before treating it as a drop-in swap.
Does the integrated Ethernet MAC support TLS or encryption offload?
The Ethernet MAC is a standard media access controller — cryptography and TLS must be handled in software on the Cortex-M7 core. The 528MHz clock headroom accommodates a software TLS stack for industrial comms, but the encryption workload competes with your application and RTOS scheduling.