NXP MIMX8MM6DVTLZAA i.MX8MM Quad-Core 1.8GHz 64-bit ARM MPU, 486-LFBGA
NXP i.MX8MM series, quad-core ARM Cortex-A53 at 1.8GHz, 64-bit, with ARM Cortex-M4 co-processor, DDR3L/DDR4/LPDDR4, GbE, USB 2.0, PCIe, MIPI-DSI, 486-LFBGA (14×14mm), 0°C to 95°C TJ, surface-mount tray, ROHS3 Active.
- 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
- Date & lot codes on quoteStated per line before you commit; label photos on request.
- MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
- PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.
Specifications
| Parameter | Value |
|---|---|
| Series | i.MX8MM |
| Mounting type | Surface Mount |
| Additional interfaces | I²C, PCIe, SDHC, SPI, UART |
| Display & interface controllers | MIPI-DSI |
| Operating temperature | 0°C ~ 95°C (TJ) |
| Number of cores (Bus width) | 4 Core, 64-Bit |
| USB | USB 2.0 + PHY (2) |
| Speed | 1.8GHz |
| Package | Tray |
| Ethernet | GbE |
| Core processor | ARM® Cortex®-A53 |
| Case | 486-LFBGA, FCBGA |
| RAM controllers | DDR3L, DDR4, LPDDR4 |
| Co-Processors (DSP) | ARM® Cortex®-M4 |
| Security features | ARM TZ, CAAM, HAB, OCRAM, RDC, SJC, SNVS |
| Graphics acceleration | Yes |
Frequently asked questions
Does the MIMX8MM6DVTLZAA support HAB secure boot for a Cortex-A53 signed firmware chain?
Yes. The device carries HAB (High-Assurance Boot) as part of its on-chip security subsystem alongside ARM TrustZone, CAAM, and SNVS. These blocks together support a Chain of Trust boot sequence that validates signed firmware at each stage — the part does not block a HAB firmware signing chain.
Are all four Cortex-A53 cores active on this MPN, and what DRAM types does the controller support?
The MIMX8MM6DVTLZAA is a 4-core, 64-bit device — all four ARM Cortex-A53 cores are available to the application. The memory controller supports DDR3L, DDR4, and LPDDR4, allowing the buyer to select the DRAM technology based on power budget and availability; DDR4 timing parameters for the boot ROM are specified in the NXP i.MX8M Mini datasheet.
What peripheral interfaces are available on this part for industrial edge node designs?
The integrated peripheral set includes GbE, USB 2.0 with two PHYs, PCIe, SDHC, SPI, I²C, and UART — enough to build a wired industrial edge node without additional PHY components. Graphics acceleration and MIPI-DSI display output are also on-chip.