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NXP Semiconductors LS1012AXE7EKA — Logic ICs

NXP LS1012AXE7EKA QorIQ Layerscape MPU

MPNLS1012AXE7EKA
End of Life

NXP QorIQ® Layerscape LS1012AXE7EKA, single-core 64-bit ARM® Cortex®-A53 MPU, 600 MHz, USB 2.0 (1) + USB 3.0 with integrated PHY, SATA 6 Gbps (1), dual GbE, DDR3L controller, Secure Boot & TrustZone, -40°C to 105°C, 211-FCLGA (9.6x9.6 mm), tray.

$38.67Ref. price · indicative, final on quote
Packaging211-VFLGA
StockContact for availability
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
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Specifications

LS1012AXE7EKA Technical Specifications
ParameterValue
SeriesQorIQ® Layerscape
Mounting typeSurface Mount
Operating temperature-40°C ~ 105°C
Number of cores (Bus width)1 Core, 64-Bit
USBUSB 2.0 (1), USB 3.0 + PHY
SATASATA 6Gbps (1)
Speed600MHz
PackageTray
EthernetGbE (2)
Core processorARM® Cortex®-A53
Case211-VFLGA
RAM controllersDDR3L
Security featuresSecure Boot, TrustZone®

Product details

What this 600 MHz single-core A53 MPU is for

The NXP LS1012AXE7EKA is a single-core 64-bit ARM Cortex-A53 microprocessor from the QorIQ Layerscape family, clocked at 600 MHz. It targets power-sensitive networking, IoT gateway, and industrial control applications where a full application processor is needed but the thermal and cost budget won't stretch to a multi-core part. The single A53 core with 64-bit datapath gives it enough headroom for a Linux control plane or a lightweight data-forwarding stack while keeping the power draw low enough for fanless enclosures.

I/O mix: USB 3.0 + PHY, SATA 6 Gbps, dual GbE

The integrated USB 3.0 port includes the PHY on-chip, saving a separate transceiver and the associated BOM cost. A second USB 2.0 port is available for lower-speed peripherals or debug. The single SATA 6 Gbps channel lets you attach an SSD or HDD directly for local storage — useful for an edge gateway that buffers sensor data. Two Gigabit Ethernet MACs are present; the buyer should verify whether the external PHY interface is RGMII or SGMII in the full datasheet, as that affects the PHY selection and PCB trace routing.

The 211-FCLGA package measures 9.6x9.6 mm — a land-grid array, not a BGA, so there are no solder balls to collapse during reflow. The LGA footprint is more forgiving for hand-assembly and rework, but the pad layout and stencil aperture still need careful design to avoid voids under the large central ground pad. Surface-mount only.

Security features: Secure Boot and TrustZone

Secure Boot and TrustZone are listed as security features. Secure Boot ensures only authenticated firmware executes from power-on, which is a hard requirement for any device that connects to the internet or a corporate network. TrustZone provides a hardware-isolated trusted execution environment for cryptographic keys and secure firmware updates. If your design needs to pass PSA Certified Level 1 or similar, this part covers the baseline hardware root of trust without an external secure element.

Lifecycle and supply posture

ROHS3 compliant.

Frequently asked questions

What interfaces does LS1012AXE7EKA integrate?

It integrates one USB 3.0 port with integrated PHY, one USB 2.0 port, one SATA 6 Gbps channel, and two Gigabit Ethernet MACs. A DDR3L memory controller is also on-chip.