Skip to main content
NXP USA Inc. LPC2134FBD64/01EL — Microcontrollers & Processors (MCU / MPU / DSP)

NXP LPC2134FBD64/01EL ARM7 MCU, 128KB Flash, 60MHz, 64-LQFP

MPNLPC2134FBD64/01EL
Active

NXP LPC2134FBD64/01EL ARM7 MCU, 128KB Flash, 16KB RAM, 60MHz core, 47 I/O, 3.3V supply, 16x10b SAR ADC + 1x10b DAC, I²C/SPI/UART/USART/SSP, internal oscillator, brown-out/POR/WDT, -40°C to 85°C, 64-LQFP (10x10mm) tray.

$22.2400Ref. price · indicative, final on quote
Packaging64-LQFP
StockContact for availability
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

LPC2134FBD64/01EL Technical Specifications
ParameterValue
SeriesLPC2100
Mounting typeSurface Mount
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))3V ~ 3.6V
Operating temperature-40°C~85°C(TA)
Speed60MHz
PackageTray
RAM size16K x 8
Core size16/32-Bit
PeripheralsBrown-out Detect/Reset, POR, PWM, WDT
ConnectivityI²C, Microwire, SPI, SSI, SSP, UART/USART
Number of i (O)47
Core processorARM7®
Case64-LQFP
Data convertersA/D 16x10b SAR; D/A 1x10b
Program memory size128KB (128K x 8)

Frequently asked questions

Does the LPC2134FBD64/01EL support standard ARM7 toolchains for in-circuit debug and Flash programming?

Yes. The ARM7 JTAG interface on this device works with Keil MDK, IAR EWARM, and GCC-based tools via OpenOCD. The 128KB Flash and 16KB RAM fit within the standard toolchain working set without extended memory model requirements.

Is there a second source or pin-compatible peer for the LPC2134FBD64/01EL?

No official cross-reference or second-source is listed in the current ledger. The 47-I/O, 64-LQFP form factor and 16x10b ADC are shared across several LPC2100 variants in the same package, but a drop-in swap requires board-level validation against the target memory map and peripheral feature set.