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NXP USA Inc. LPC11U68JBD48K — Microcontrollers & Processors (MCU / MPU / DSP)

NXP LPC11U68JBD48K MCU, ARM Cortex-M0+ 50MHz, 256KB Flash, USB, 48-LQFP

MPNLPC11U68JBD48K
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NXP LPC11Uxx series, 32-bit ARM Cortex-M0+ at 50MHz, 256KB Flash, 36KB RAM, 4KB EEPROM, USB/I2C/SPI/SSP/UART, 8×12-bit SAR ADC, 34 I/O, -40°C to 105°C, 2.4–3.6V, 48-LQFP (7×7mm) Tray.

$8.9800Ref. price · indicative, final on quote
Packaging48-LQFP
StockContact for availability
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
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Specifications

LPC11U68JBD48K Technical Specifications
ParameterValue
SeriesLPC11Uxx
Mounting typeSurface Mount
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))2.4V ~ 3.6V
Operating temperature-40°C~105°C(TA)
Speed50MHz
PackageTray
RAM size36K x 8
Core size32-Bit Single-Core
EEPROM size4K x 8
PeripheralsBrown-out Detect/Reset, DMA, POR, PWM, WDT
ConnectivityI²C, Microwire, SmartCard, SPI, SSP, UART/USART, USB
Number of i (O)34
Core processorARM® Cortex®-M0+
Case48-LQFP
Data convertersA/D 8x12b SAR
Program memory size256KB (256K x 8)

Frequently asked questions

Does the LPC11U68JBD48K support SWD debug and which ARM toolchains are validated for LPC11Uxx?

The LPC11Uxx series supports SWD debug via the ARM CoreSight debug interface — Keil MDK, IAR Embedded Workbench, and GCC (via OpenOCD or J-Link) are the three toolchains NXP validates for this family. Confirm the LPC11U68JBD48K-specific device pack is loaded in your IDE before flashing.

What is the minimum VDD operating range — does it sit comfortably on a 3.3V ±5% industrial rail?

The minimum supply is 2.4V. A 3.3V ±5% rail (3.135–3.465V) sits well inside the 2.4–3.6V operating window — no level-shifting needed. Watch brown-out: the rail must not sag below 2.4V during USB transmit bursts or motorised IO switching events; the on-chip BOD peripheral should be configured to catch those dips before firmware runs off the rails.

How does the LPC11U68JBD48K compare to the LPC11U37JBD48K on ADC and I/O?

Both carry the same 8×12-bit SAR ADC and the same 48-LQFP pin count — the I/O budget is 34 on both. The memory delta is the selection driver: the LPC11U68JBD48K doubles the Flash to 256KB and bumps RAM to 36KB versus the LPC11U37JBD48K's lower tiers. If the existing layout is locked, the ADC and I/O count are a straight carry-over; recompile is required for the memory change.