28 ns propagation delay – what it means for bus timing
The maximum propagation delay is 28 ns at 4.5 V with a 50 pF load. Quiescent current is a maximum of 2 µA, which matters for battery-backed or always-on domains where the gate sits idle most of the time. The output drive is symmetric at 4 mA sink and source, enough to drive one or two standard CMOS loads but not a long backplane trace or a high-capacitance bus.
