Triple unbuffered inverter — 74HC logic, 2V to 6V rail
The NXP 74HC3GU04GD,125 is a triple unbuffered inverter in the 74HC family, providing three independent inverting gates with a single input each.
Switching speed and drive — 5 ns at 6V, 5.2 mA per output
Maximum propagation delay is 5 ns at 6V supply with a 50 pF load — the timing budget for a 20 MHz clock tree or a fast data path stays tight. The 5.2 mA output drive (both high and low) is enough to switch a downstream CMOS gate or drive a short PCB trace without a buffer. Quiescent current maxes at 20 µA — negligible for a battery-powered sensor node that spends most of its time in a static logic state. The input logic thresholds scale with supply: low at 0.5V to 1.8V, high at 1.5V to 4.2V, so the inverter triggers cleanly on standard 3.3V or 5V logic levels.
Package and board-fit — 8-XSON (2x3 mm), 0.5 mm pitch
Surface-mount assembly with MSL (Moisture Sensitivity Level) per JEDEC — the 8-XSON package is typically MSL 1, but verify the reel date code for bake requirements before reflow. The narrow 0.5 mm pitch demands a solder paste inspection step to catch bridging between adjacent pins.
Active production — sourcing and compliance
No official second-source or pin-compatible alternative is listed for this exact order code. The 74HC family includes other triple-gate variants (e.g., 74HC3G04 for buffered output), but the unbuffered topology of the 3GU04GD means the output slew rate is not shaped — a consideration for signal-integrity-sensitive traces.