What this dual decade ripple counter does
The NXP 74HC390PW,112 is a dual decade ripple counter in the 74HC family, containing two independent 4-bit decade counters per package. Each counter counts down on the negative edge of the clock input, with an asynchronous master reset that clears all outputs to zero. The 71 MHz maximum count rate sets the upper limit for frequency division and event counting in your timing chain.
At 71 MHz, this counter can divide a 71 MHz clock down to 7.1 MHz (decade division) or lower with cascaded stages. For a 50 MHz system clock, you have 21 MHz of headroom before the counter misses edges — useful for frequency synthesis, time-base generation, or event counting in high-speed industrial encoders. The negative-edge trigger means the counter advances on the falling edge, which affects setup/hold timing relative to other logic in the same clock domain.
Package and footprint fit
The 16-TSSOP body is 4.40 mm wide with a 0.65 mm lead pitch. This is a standard TSSOP-16 footprint; the same land pattern accepts 74HC393 or 74HC161 variants in the same package, simplifying PCB reuse. No exposed pad — all dissipation goes through the leads, so keep the ambient below 125°C for the full 71 MHz operation.
Lifecycle and compliance
The 74HC series is a mature logic family with broad second-source availability — TI, ON Semiconductor, and others offer functionally equivalent parts in the same TSSOP-16 footprint.