Skip to main content
NXP Semiconductors 74AUP1G386GN,132 — Discrete Semiconductors

NXP 74AUP1G386GN,132 XOR Gate, 3-Input, 0.8-3.6V

MPN74AUP1G386GN,132
End of Life

NXP Semiconductors 74AUP series, Logic Gate, XOR (Exclusive OR), 1 Circuit, 3 Inputs, 6-XFDFN, Surface Mount, 0.8V ~ 3.6V supply, -40°C ~ 125°C.

$0.17Ref. price · indicative, final on quote
Packaging6-XFDFN
StockContact for availability
Lead timeIn Stock wk
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

74AUP1G386GN,132 Technical Specifications
ParameterValue
Series74AUP
Logic typeXOR (Exclusive OR)
Mounting typeSurface Mount
Voltage0.8V ~ 3.6V
Current - quiescent500 nA
Current - output high, low4mA, 4mA
Number of inputs3
Operating temperature-40°C ~ 125°C
PackageBulk
Case6-XFDFN
Number of circuits1
Input logic level - low0.7V ~ 0.9V
Input logic level - high1.6V ~ 2V
Max propagation delay @ v, max CL6.1ns @ 3.3V, 30pF

Product details

Supply flexibility and signal integrity at 3.3 V

The 74AUP1G386GN,132: At 3.3 V with a 30 pF load, the maximum propagation delay is 6.1 ns — fast enough for control signals and status polling in sub-100 MHz digital paths. Output drive is rated at 4 mA source and 4 mA sink, sufficient to drive a single CMOS load or a short PCB trace without external buffering. The 3-input XOR function (Y = A ⊕ B ⊕ C) is useful for parity generation, data comparison, or as a controlled inverter in a clock or data path.

6-XSON package and industrial temperature range

Housed in a 6-XSON (0.9 x 1.0 mm) package — the supplier device package is 6-XSON (0.9x1) — this is a very small footprint for space-constrained PCBs. The 500 nA quiescent max holds across the full temperature range, so the battery drain does not climb with temperature as it would in a higher-power logic family.