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NXP USA Inc. MKL05Z32VFM4 — Microcontrollers & Processors (MCU / MPU / DSP)

NXP MKL05Z32VFM4 MCU — 48MHz Cortex-M0+ 32KB Flash 32QFN

MPNMKL05Z32VFM4
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NXP Kinetis KL0 series, ARM Cortex-M0+ core at 48MHz, 32KB Flash, 4KB RAM, 14-channel 12-bit A/D and 1-channel 12-bit D/A converters, 28 I/O, surface-mount 32-HVQFN (5×5mm) wettable flank, tray, -40°C to 105°C operating temperature, ROHS3 compliant.

$4.2500Ref. price · indicative, final on quote
Packaging32-VFQFN Exposed Pad
StockContact for availability
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

MKL05Z32VFM4 Technical Specifications
ParameterValue
SeriesKinetis KL0
Mounting typeSurface Mount, Wettable Flank
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))1.71V ~ 3.6V
Operating temperature-40°C ~ 105°C (TA)
Speed48MHz
PackageTray
RAM size4K x 8
Core size32-Bit Single-Core
PeripheralsBrown-out Detect/Reset, DMA, LVD, POR, PWM, WDT
ConnectivityI²C, SPI, UART/USART
Number of i (O)28
Core processorARM® Cortex®-M0+
Case32-VFQFN Exposed Pad
Data convertersA/D 14x12b; D/A 1x12b
Program memory size32KB (32K x 8)

Frequently asked questions

Is the MKL05Z32VFM4 drop-in compatible with the MKL05Z16 in the same 32-HVQFN package?

Mechanically yes — same pinout and package. Flash size does not affect pinout. The step up from 16KB to 32KB Flash requires only a firmware rebuild against the correct device header; no schematic or layout change.

Are any of the 28 GPIOs 5V-tolerant for direct connection to 24V industrial sensors?

No — the I/O voltage domain is tied to VDD at 1.71V to 3.6V. KL-series GPIOs are not 5V-tolerant on this supply range. Interfacing to 24V signals requires external level-shifting or clamping.

Can the 14-channel 12-bit ADC run continuously via DMA while PWM outputs update independently?

Structurally yes — the DMA controller moves ADC results to SRAM autonomously, and PWM runs on its own hardware timer. Bus contention under simultaneous heavy peripheral load is a function of clock configuration detailed in the device datasheet, not an architectural block.