NXP LPC54113J256BD64QL Dual-Core MCU, 100 MHz, 256 KB Flash, 64-LQFP
NXP LPC54113J256BD64QL, 32-bit ARM Cortex-M4/M0+ dual-core at 100 MHz, 256 KB flash, 192 KB RAM, 48 I/O, USB OTG, I²C/SPI/UART, 12-channel 12-bit ADC, 1.62–3.6 V, -40 to 105 °C, ROHS3, 64-LQFP.
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Specifications
| Parameter | Value |
|---|---|
| Series | LPC54100 |
| Mounting type | Surface Mount |
| Oscillator type | Internal |
| Program memory type | FLASH |
| Voltage - supply (Vcc (Vdd)) | 1.62V ~ 3.6V |
| Operating temperature | -40°C~105°C(TA) |
| Speed | 100MHz |
| Package | Tray |
| RAM size | 192K x 8 |
| Core size | 32-Bit Dual-Core |
| Peripherals | Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT |
| Connectivity | I²C, SPI, UART/USART, USB |
| Number of i (O) | 48 |
| Core processor | ARM® Cortex®-M4/M0+ |
| Case | 64-LQFP |
| Data converters | A/D 12x12b |
| Program memory size | 256KB (256K x 8) |
Frequently asked questions
Is the LPC54113 firmware-compatible with an LPC54102 project built under IAR EWARM 8.40?
Both parts share the same ARM Cortex-M4/M0+ core architecture and LPC54100 peripheral set, so source-level compatibility is high — but the M0+ core on the 54113 runs its own flash bootloader region that may require a separate build section. Check the NXP SDK linker script for the M0+ memory partition before migrating a project.
The peer 64-pin LPC54100 variant lists 32 I/O — does the 48-I/O count on this part require a layout spin?
The 48 I/O on the 64-LQFP maps additional pins to GPIO and analog channels beyond the 32-I/O variant. Standard debug and trace pins are present on both; NXP's SDK pin-muxing tool handles the extra signals, so a full layout spin is not required — verify your pin-assignment toolchain against the NXP SDK for this specific package variant.