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NXP USA Inc. LPC54102J256UK49Z — Microcontrollers & Processors (MCU / MPU / DSP)

NXP LPC54102J256UK49Z MCU, ARM Cortex-M4/M0+ Dual-Core, 100MHz

MPNLPC54102J256UK49Z
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NXP LPC54100 series, LPC54102J256UK49Z, ARM Cortex-M4/M0+ dual-core 32-bit MCU, 100MHz, 256KB Flash, 104KB RAM, 39 I/O, 12-ch 12-bit ADC, I²C/SPI/UART, 1.62V-3.6V, -40°C to 105°C, 49-WLCSP (3.29×3.29mm), surface mount, active ROHS3.

$10.4800Ref. price · indicative, final on quote
NXP USA Inc. LPC54102J256UK49Z datasheet (PDF)
Packaging49-UFBGA, WLCSP
RoHSROHS3 Compliant
SeriesLPC54100
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

LPC54102J256UK49Z specifications
ParameterValue
SeriesLPC54100
MountingSurface Mount
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))1.62V ~ 3.6V
Operating temperature-40°C~105°C(TA)
Speed100MHz
PackageTape & Reel (TR); Cut Tape (CT)
RAM size104K x 8
Core size32-Bit Dual-Core
PeripheralsBrown-out Detect/Reset, POR, PWM, WDT
ConnectivityI²C, SPI, UART/USART
Number of i (O)39
Core processorARM® Cortex®-M4/M0+
Case49-UFBGA, WLCSP
Data convertersA/D 12x12b
Program memory size256KB (256K x 8)

Product details

Dual-core 100 MHz MCU for sensor fusion and audio

The NXP LPC54102J256UK49Z is a 32-bit dual-core microcontroller built around an ARM Cortex-M4 and Cortex-M0+ running at 100 MHz. It packs 256 KB of Flash and 104 KB of RAM, with 39 general-purpose I/O lines and a 12-channel 12-bit ADC. The part targets always-on sensor processing, voice activation, and low-power audio pipelines where the M0+ handles background tasks while the M4 wakes for heavy compute.

Supply range of 1.62 V to 3.6 V.

49-WLCSP package — board integration note

The 49-WLCSP (3.29×3.29 mm) is a wafer-level chip-scale package. It requires a controlled solder-paste stencil and X-ray inspection after reflow.

Frequently asked questions

What is the listed speed of LPC54102J256UK49Z?

The core clock speed is 100 MHz on both the Cortex-M4 and Cortex-M0+ cores.