NXP LPC1342FHN33,518 — ARM Cortex-M3 MCU, 72MHz, 16KB Flash, USB
NXP LPC1342FHN33,518 — 32-bit ARM Cortex-M3 MCU, 72MHz, 16KB Flash, 4KB SRAM, USB device/OTG, I²C/SPI/SSP/UART, 28 I/O, 32-VQFN exposed pad (7×7mm), -40°C to 85°C, 2V–3.6V, Tape & Reel.
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Specifications
| Parameter | Value |
|---|---|
| Series | LPC13xx |
| Mounting type | Surface Mount |
| Oscillator type | Internal |
| Program memory type | FLASH |
| Voltage - supply (Vcc (Vdd)) | 2V ~ 3.6V |
| Operating temperature | -40°C ~ 85°C (TA) |
| Speed | 72MHz |
| Package | Tape & Reel (TR) |
| RAM size | 4K x 8 |
| Core size | 32-Bit Single-Core |
| Peripherals | Brown-out Detect/Reset, POR, WDT |
| Connectivity | I²C, Microwire, SPI, SSI, SSP, UART/USART, USB |
| Number of i (O) | 28 |
| Core processor | ARM® Cortex®-M3 |
| Case | 32-VQFN Exposed Pad |
| Data converters | A/D 8x10b |
| Program memory size | 16KB (16K x 8) |
Frequently asked questions
Does the 32-VQFN exposed pad require thermal vias to the ground plane?
Yes — the exposed pad must be soldered to a thermal land under the device for rated thermal performance. The specific θJA values for still air versus forced convection are datasheet parameters not carried in the summary ledger.
Can all 28 I/O pins be used as GPIO if USB is not populated?
The two pins shared with USB D+/D- become available as standard GPIO in non-USB builds — no board respin is required for that reallocation. All other peripherals route independently.
Is the 4KB SRAM sufficient for a USB CDC/Virtual COM driver at 72MHz?
It is tight but workable — a USB CDC driver with ISR buffers can consume 1.5–2KB, leaving 2–2.5KB for application code. Exact contiguous SRAM availability for USB device operation is a register-level datasheet detail, not a ledger field.