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NXP USA Inc. LPC1112FHN33/102,5 — Microcontrollers & Processors (MCU / MPU / DSP)

NXP LPC1112FHN33/102,5 ARM Cortex-M0 MCU, 50 MHz, 16 KB Flash

MPNLPC1112FHN33/102,5
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NXP LPC1100L series 32-bit ARM Cortex-M0 MCU, LPC1112FHN33/102,5, 50 MHz, 16 KB Flash, 2 KB SRAM, 28 I/O, I²C/SPI/UART, 8x10-bit ADC, 1.8-3.6 V, -40 to 85 °C, 32-HVQFN.

$3.3800Ref. price · indicative, final on quote
StockContact for availability
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

LPC1112FHN33/102,5 Technical Specifications
ParameterValue
SeriesLPC1100L
Mounting typeSurface Mount
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))1.8V ~ 3.6V
Operating temperature-40°C ~ 85°C (TA)
Speed50MHz
PackageTray
RAM size2K x 8
Core size32-Bit Single-Core
PeripheralsBrown-out Detect/Reset, POR, WDT
ConnectivityI²C, SPI, UART/USART
Number of i (O)28
Core processorARM® Cortex®-M0
Case32-VQFN Exposed Pad
Data convertersA/D 8x10b
Program memory size16KB (16K x 8)

Product details

Supply voltage and on-chip resources

Operates from 1.8 V to 3.6 V. The internal oscillator and brown-out detect / POR / watchdog peripherals reduce external BOM count.

Sourcing and lifecycle

Listed as Active in production — no last-time-buy or obsolescence notice on this line. Sourced and quoted to order against an RFQ through independent distribution; availability and current pricing confirmed at quote time.

Frequently asked questions

What is the core speed of LPC1112FHN33/102,5?

The ARM Cortex-M0 core runs at 50 MHz, which is the maximum clock for this device.

What is the memory configuration of LPC1112FHN33/102,5?

It has 16 KB of Flash program memory and 2 KB of SRAM, organized as 16K x 8 and 2K x 8 respectively.