13824 logic cells and 600K gates — partition sizing
The Microchip AGL600V2-FGG144I is a nonvolatile IGLOO FPGA with 13824 logic cells and 600000 system gates. The 110592 bits of embedded RAM give you about 8 bits per logic cell — enough for modest FIFO or register-file instantiation, but a design that needs block RAM for large frame buffers will push against the 108 Kbit ceiling.
1.14 V core — single-rail simplicity
The core supply is 1.14 V nominal, which means a single 1.2 V rail powers the fabric. That simplifies the power-tree BOM compared to older 1.5 V or 1.8 V FPGAs — one LDO or buck converter instead of two. The I/O banks still need their own 1.8 V or 3.3 V rail depending on the interface standard.
97 I/O in a 144-ball BGA — fan-out planning
The 144-ball FBGA (0.80 mm pitch) brings out 97 user I/O. That leaves 47 balls for power and ground — a solid ratio for signal integrity. The 0.80 mm pitch is manageable on a 4-layer board with blind vias; a 2-layer board will struggle to route all 97 signals without breaking the escape pattern.
The nonvolatile flash fabric holds configuration instantly on power-up — no external configuration memory or boot time.
The buyer can place this on the BOM without planning a qualification of a replacement part in the next 12–18 months.