The Microchip AGL250V5-FGG144I is a member of the IGLOO series of low-power flash-based FPGAs. It packs 250000 system gates, 6144 logic cells, and 36864 bits of embedded SRAM in a 144-ball FPBGA package measuring 13x13 mm. The core runs from a single 1.5V supply (1.425V to 1.575V), and the 97 user I/O are configurable for various single-ended and differential standards.
6144 logic cells and 97 I/O — sizing the BOM fit
With 6144 logic cells and 97 I/O, this part sits in the small-to-mid density tier of the IGLOO family. It is sized for glue logic consolidation, sensor interface aggregation, or a modest state machine that would otherwise eat a handful of 74-series parts and a CPLD. The 36 Kbit SRAM (36864 bits) is enough for a small FIFO, a register file, or a coefficient lookup table — not enough for a frame buffer or large packet queue. If your design needs more than that, the IGLOO2 family (e.g. M2GL025) steps up to 1.1 Mbit SRAM and 27696 logic cells, but in a different footprint and with a 1.14V core.
Supply rails and power-up sequencing
The flash-based fabric powers up instantly — no external configuration memory or boot time — which matters for applications that need the I/O to be valid before the system controller finishes its own reset sequence. The 1.5V rail should be within ±5% (1.425V to 1.575V); a standard 1.5V LDO with 200 mV dropout at the load current will hold regulation through a 1.2V brown-out on the input.
Package and board-level handling
That means via-in-pad or microvias are not mandatory, but the escape routing under the BGA needs careful planning.