MAX II CPLD for industrial glue logic
The Intel EPM240F100I5N is a MAX® II CPLD with 240 logic elements and 192 macrocells, packaged in a 100-LBGA (11x11 mm) footprint. It provides 80 user I/O and a propagation delay of 4.7 ns.
4.7 ns tpd — timing margin for fast buses
The 4.7 ns pin-to-pin delay is the headline timing spec. The device is in-system programmable (ISP), allowing logic updates post-assembly.
The EPM240F100I5N carries an end-of-life (eol_hot) lifecycle stage. While the manufacturer lists the product status as Active, the eol_hot flag signals that a last-time-buy window may be approaching or in effect. For new designs, the commercial-temperature sibling EPM240F100C5N (0°C to 85°C) is a functional alternative if the temperature range permits.