Clock distribution for 133 MHz buses
The Infineon W163-15G is a PLL-based Zero Delay Buffer from the Spread Aware™ family, designed to regenerate a clock input with matched phase alignment across five outputs. Its 133 MHz maximum frequency suits it for distributing clocks in 100 MHz or 133 MHz memory and logic buses where skew between the input and each output must stay within a few hundred picoseconds.
Operating from a 2.97 V to 3.63 V supply, the device is a direct fit for 3.3 V ±10 % rails common in networking and computing platforms.
PLL architecture and bypass mode
The integrated PLL includes a bypass path, allowing the device to operate either as a synthesized clock source with zero-delay alignment or as a simple buffer that passes the input clock through without frequency multiplication. The 1:5 input-to-output ratio provides five low-skew copies of the reference clock, sufficient for driving multiple SDRAM DIMMs, PCI slots, or Ethernet PHY reference inputs on a single board.
The surface-mount package is compatible with reflow soldering profiles typical for lead-free assemblies, though the device itself is marked RoHS non-compliant per the manufacturer's declaration.