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Infineon Technologies CYDMX128A16-65BVXIKB — Discrete Semiconductors

Infineon CYDMX128A16-65BVXIKB SRAM, 128Kbit, 65ns, 100-VFBGA

MPNCYDMX128A16-65BVXIKB
End of Life

Infineon Technologies CYDMX128A16-65BVXIKB dual-port asynchronous SRAM, 128Kbit (8K x 16), 65 ns access time, parallel interface, 100-VFBGA (6x6 mm), -40°C to +85°C.

$6.95Ref. price · indicative, final on quote
Packaging100-VFBGA
RoHSNot applicable
Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CYDMX128A16-65BVXIKB specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Voltage1.7V ~ 1.9V, 2.4V ~ 2.6V, 2.7V ~ 3.3V
Memory interfaceParallel
Operating temperature-40°C ~ 85°C (TA)
PackageBulk
TechnologySRAM - Dual Port, Asynchronous
Access time65 ns
Memory size128Kbit
Memory formatSRAM
Case100-VFBGA
Memory organization8K x 16
Write cycle time - word, page65ns

Product details

Dual-port SRAM with multiple supply rails

The Infineon CYDMX128A16-65BVXIKB is a 128Kbit dual-port asynchronous SRAM organised as 8K x 16 bits, with a 65 ns access time across the full operating range. It accepts three separate supply voltage bands — 1.7V–1.9V, 2.4V–2.6V, and 2.7V–3.3V — allowing the core and I/O to run at different levels without an external level shifter on the address and data bus.

Board-fit and temperature grade

Housed in a 100-ball VFBGA (6x6 mm body), the package footprint suits dense PCB layouts where board space is at a premium — the fine-pitch BGA demands careful fan-out via microvias on a multi-layer board.

Active production and sourcing posture

Sourced through independent distribution channels, each unit is verified for date-code consistency and marking integrity before shipment — the laser etch is a fingerprint, and we check it traces cleanly to Infineon's plant records.

Parallel interface and write timing

The memory interface is parallel, with a write cycle time matching the 65 ns access — word and page writes complete in the same cycle, simplifying the timing budget in a synchronous system.