45 ns byte-wide SRAM for 8-bit buses
The CY62128EV30LL-45SXI: For an 8-bit MCU or a FIFO buffer running at typical bus speeds, 45 ns sets the read-cycle ceiling — the processor must stretch its wait states if it clocks faster than ~22 MHz on consecutive reads. The industrial temperature grade (-40 to +85 °C) covers factory-floor, outdoor telecom cabinet, and unheated enclosure deployments.
Housed in a 32-SOIC (0.445-inch body width, 11.30 mm), the same footprint used by legacy 128K x 8 SRAMs from multiple vendors. Supplied in tube. The write cycle time matches the read access at 45 ns — byte-wide writes complete in one cycle with no page-mode or burst overhead.
ROHS3 compliant, with no exemption-based restrictions that would block EU or California market entry. The part belongs to the MoBL (Motherboard Battery-Less) series — Infineon's low-power asynchronous SRAM family characterized by reduced standby current.