The CY23S09ZXC-1H is a zero delay buffer with a 1:9 fanout ratio, designed to distribute a single LVCMOS or LVTTL input clock to nine LVCMOS outputs while maintaining phase alignment. The integrated PLL includes a bypass mode, allowing the input clock to pass directly to the outputs when the PLL is not required for zero-delay synchronization. Maximum output frequency is 133.33 MHz, making it suitable for clock distribution in systems with moderate-speed digital logic, such as FPGAs, ASICs, or memory controllers.
Rated for the commercial temperature range of 0°C to 70°C, which covers most indoor equipment, networking gear, and test instrumentation — but not extended industrial or automotive environments.