Infineon CY2302SI-1 PLL-based clock driver, zero-delay buffer, 133 MHz max, 1:2 LVCMOS output, dual 3.3 V / 5 V supply, -40°C to 85°C, 8-SOIC package.
| Parameter | Value |
|---|---|
| Type | Frequency Multiplier, Zero Delay Buffer |
| Mounting | Surface Mount |
| Voltage | 3.135V ~ 3.465V, 4.5V ~ 5.5V |
| Frequency | 133MHz |
| Operating temperature | -40°C ~ 85°C (TA) |
| PLL | Yes |
| Input | LVCMOS, LVTTL |
| Output | LVCMOS |
| Package | Bulk |
| Case | 8-SOIC (0.154\", 3.90mm Width) |
| Divider (Multiplier) | Yes/Yes |
| Number of circuits | 1 |
| Ratio - Input:Output | 1:2 |
| Differential - Input:Output | No/No |
The CY2302SI-1 integrates a PLL that multiplies and aligns the output clock edges to the input with zero propagation delay — it is a frequency multiplier and zero-delay buffer in one 8-SOIC package. Maximum output frequency is 133 MHz. The 1:2 fanout ratio drives two loads from one input without external fanout buffers.
Packaged in 8-SOIC (0.154" width, 3.90 mm body), surface-mount.
Yes.
133 MHz. This is the PLL's upper lock limit; the output frequency equals the input frequency multiplied by the internal divider/multiplier ratio.