Signal-level bridge for high-speed backplanes
It handles two channels per circuit, making it a compact fit for clock or data lines where the signal standard changes between a source and a load — common in telecom line cards, FPGA-to-serdes links, and test equipment backplanes.
The input flexibility is the headline feature: the part accepts CML, HSTL, LVDS, and LVPECL without external level-setting resistors, so a single BOM line covers multiple interface standards. The LVPECL output provides the edge rates needed for clock distribution above 1 GHz — important for timing margin in high-speed ADC or SerDes clock trees. With one circuit and two channels, this part is sized for point-to-point links, not multi-drop buses. The 10-uMAX package (3.00 mm width) fits tight channel spacing on a dense board.