Three-rail monitoring in a five-pin package
The MAX6743XKSDD3+ monitors three independent voltage rails and asserts a single active-low reset when any rail falls below its threshold. This is the part for a multi-voltage board — FPGA core, I/O, and auxiliary — where a single supervisor IC replaces three discrete reset generators. The push-pull output eliminates the external pull-up resistor that open-drain supervisors need.
Reset timing and temperature range
Reset timeout is a minimum of 150 ms — long enough for the downstream processor to finish its power-on sequence before the supervisor releases the reset line. The push-pull output holds the reset state without a pull-up, simplifying the BOM on the processor's reset input. Surface-mount assembly is standard for this package class.