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Analog Devices MAX6719UTZWD3 — Power Management (PMIC / Gate Driver)

MAX6719UTZWD3 Multi-Voltage Supervisor, SOT-23-6, Active

MPNMAX6719UTZWD3
End of Life

Maxim Integrated MAX6719UTZWD3, Multi-Voltage Supervisor, 3 channels, thresholds 1.665V, 2.313V, Adj, active-low open-drain reset, 140ms min timeout, SOT-23-6, -40°C to 85°C.

$2.74Ref. price · indicative, final on quote
Analog Devices MAX6719UTZWD3 datasheet (PDF)
PackagingSOT-23-6
RoHSRoHS non-compliant
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

MAX6719UTZWD3 specifications
ParameterValue
TypeMulti-Voltage Supervisor
MountingSurface Mount
Voltage - threshold1.665V, 2.313V, Adj
Number of voltages monitored3
Operating temperature-40°C ~ 85°C (TA)
ResetActive Low
OutputOpen Drain or Open Collector
PackageBulk
Reset timeout140ms Minimum
CaseSOT-23-6

Product details

It does not carry an AEC-Q100 automotive grade, so it is not specified for under-hood or passenger-safety applications. The operating range is sufficient for most embedded systems that are not exposed to engine-bay heat cycles.

RoHS status — a sourcing gate

This part is RoHS non-compliant. It contains lead above the threshold, typically in the solder finish or die-attach material.

Because it is active, there is no urgency to find a drop-in replacement for new designs, though the RoHS constraint may push some buyers to the lead-free variant.

Frequently asked questions

Can MAX6719UTZWD3 replace MAX6719UTZWD2?

The MAX6719UTZWD2 and MAX6719UTZWD3 are both multi-voltage supervisors in the same SOT-23-6 package and pinout, but they differ in the fixed threshold voltages. The MAX6719UTZWD2 uses a different set of fixed thresholds. Check the threshold table in the datasheet to confirm the replacement covers your rail voltages. If the thresholds match your rails, the parts are pin-compatible.

What is the reset timeout of MAX6719UTZWD3?

The reset timeout is a minimum of 140ms. This is a standard duration that ensures the monitored rails have stabilized before the system microcontroller or FPGA is released from reset, covering most power-up sequencing requirements.